The present invention relates to a method and circuit for the generation of the voltage for the programming and erasure of a non-volatile memory cell. The invention can be applied in the field of non-volatile programmable and electrically erasable memories (including but not limited to EPROMs, EEPROMs and flash memories).
The memory cells of these memories are based on a technology that makes use of floating-gate transistors. For the programming or erasure of a memory cell of this kind, it is necessary to produce high voltages of about 15 to 20 volts. These voltages are given either by an external voltage source or internally by a load pump integrated into the memory. The programming or erasure voltage applied to a memory cell is shown in FIG. 1. It conventionally has:
an initial bias at the supply voltage Vcc of the memory constituting a first voltage plateau 10; PA1 a voltage ramp constituted by a rising phase 11 during which the voltage climbs linearly up to a high voltage V.sub.H and by a voltage plateau 12; and PA1 a voltage drop 13 during which the voltage returns to the value of the initial voltage. PA1 either a load pump with high fan-out is provided; PA1 or a voltage ramp is chosen with a slope small enough for the relationship (1) to be always verified whatever the capacitive charge addressed.
The rising phase of the voltage ramp is characterized by its slope which is governed by two conditions. First, it should not be excessively high so as not to cause stress on the gate oxide of the cell that is addressed. Indeed, it is indispensable that, during the rising phase, the electrical field within the addressed cell should not vary with excessive suddenness to avoid embrittling and possibly seven damaging the gate oxide of the cell. Second, the build-up time of the voltage ramp must be calculated so that the capacitive charge addressed in the memory does not act on the slope of the ramp. For this purpose, the fan-out S of the load pump responsible for giving the high voltage to the voltage-ramp generation circuit should be greater than the addressed capacitive charge C multiplied by the slope of the ramp, namely it is necessary that: EQU S&gt;C*dV/dt (1)
If this relation is not verified, the slope of the ramp is not controlled and the voltage applied to the memory cell to be written is no longer controlled. The capacitive charge addressed varies as a function of the number of memory cells written simultaneously. The capacitive charge is therefore different depending on whether the memory works in normal mode (byte mode), page mode or global mode.
There are two possible methods by which it can be seen to it that the relationship (1) is always verified:
However, these two methods have certain drawbacks. With regard to the first method, it is not always possible to increase the fan-out of the load pump. Indeed, the load pump is conventionally a Schenkel pump whose fan-out is proportional to C.sub.e *f/n where C.sub.e designates the capacitance of a stage of the pump, f designates the pumping frequency and n designates the number of stages of the pump. Increasing the fan-out of the pump makes it necessary to reduce the number of stages n, which is not possible for n fixes the voltage delivered by the pump, or else to increase C.sub.e or f, which is very costly in terms of space taken up on silicon. As for the second method, it entails penalties with respect to memory cell write time and, hence, with respect to the speed of the memory. In particular, it penalizes the operation of the memory in normal mode as compared with the operation in page mode or in global mode.